The present invention relates to a technology effectively applicable to a method of controlling the internal conditions of a non-volatile memory which can electrically write or erase memory information, and more specifically to the technology effectively applicable, for example, to a flash memory.
A flash memory uses, as a memory cell, a non-volatile memory device consisting of a double-gate structure MOSFET having a control gate and a floating gage and a threshold voltage of MOSFET can be varied to store information by changing a fixed amount of charges of the floating gate.
In such flash memory, change of the threshold voltage due to the write and erase operations to the memory cells fluctuates in respective operations depending on the operating conditions such as environment temperature even when the memory cells of the same kind having the identical characteristics are used and therefore the threshold voltages after the write and erase operations are distributed within a certain range. Moreover, a certain memory cell cannot vary the threshold voltage thereof up to the desired level with the single write and erase operation. Therefore, in the flash memory, a status register is generally provided therein to form the structure that if write and erase operations are not conducted accurately, such operations are stored as the write error and erase error.
A CPU which gives instruction of write and erase operations to the flash memory refers to the status register and registers the sector including a memory cell having generated an error as a defective sector and executes the process to remove such sector from the effective memory region of successive data.
However, a certain memory cell having generated the error explained above cannot vary the threshold voltage up to the desired level even after the write and erase operations are repeated, but another memory cell can conduct normal write operation when the write operation is repeated again after the data is once erased (hereinafter, such error is referred to as an accidental fault). Particularly, in a multi-level flash memory for storing the data of 2-bit or more within only one memory cell, the range of threshold voltage corresponding to each memory information is narrower than that of the two-level memory and therefore such accidental error is generated easily.
However, in the flash memory of the prior art, detail error conditions of the sector having the bit where the write error has occurred have been never reflected on the status register. Therefore, it has become apparent that the sectors having generated error are all registered as the defective sectors and removed from the effective memory area, thereby resulting in the problem that the memory capacity of the memory as a whole is reduced.
It is therefore an object of the present invention to prevent reduction of memory capacity due to the accidental write error, in a non-volatile semiconductor device enabling electrical write and erase operations such as a flash memory.
It is another object of the present invention to easily analyze a fault such as write error, in a non-volatile semiconductor device enabling electrical write and erase operations such as a flash memory.
The aforementioned and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
The typical inventions of those disclosed in the present specification will be briefly explained below.
Namely, a bit indicating whether the access can be made from the external side of a chip or not, a bit indicating whether the write operation is completed normally or not and a bit indicating whether normal write operation is possible or not by executing again the write operation are provided in the status register within the non-volatile semiconductor memory device.
In more practical, a non-volatile semiconductor memory device comprising a plurality of memory cells for storing information depending on difference of the threshold voltage by changing this threshold voltage through application of the predetermined voltage to the selected memory cells and a status register indicating the internal conditions of a chip. The status register comprises a first bit indicating whether access can be made from external side of the chip or not, a second bit indicating whether the write operation is completed normally or not, and a third bit indicating whether the normal write operation is possible or not by executing again the write operation, and conditions of these bits can be outputted to the external terminal of the chip.
According to the means explained above, the chance for normal write operation can be increased even in the memory cell that has once generated a fault by reading the contents of the status register and then conducting the write operation again depending on the conditions of bits and thereby reduction of effective memory capacity due to the accidental write error can be prevented.
Moreover, the write operation to above memory cell is performed by once erasing the threshold voltage of the selected memory cell and then changing such threshold voltage to the voltage corresponding to the write condition depending on the write information. The third bit explained above is set to the condition indicating generation of an error in such a case that the threshold voltage of the memory cell to which the information is written exceeds the predetermined voltage range. Since the selected memory cell is once erased before the write operation, the write control sequence is simplified and moreover the third bit indicating whether the normal write operation is possible or not can be set easily by executing again the write operation.
In addition, the third bit is set to indicate generation of error in such a case that the threshold voltage of memory cell exceeds the predetermined voltage range of the threshold voltage corresponding to the write operation after the write operation to the selected memory cell has been executed exceeding the predetermined number of times. With such structure, the time required for single write operation can be limited and thereby the external control device such as CPU for making access to the relevant memory device can be protected from the long-term waiting condition.
The second bit is set to indicate generation of error in such a case that threshold voltage exceeds the predetermined voltage range of the threshold voltage in the erasing condition during the verify read operation that is conducted immediately after the threshold voltage of the selected memory cell is once erased. Since a memory cell that is determined by the verify operation to be defective becomes a defective cell with higher possibility even after the write operation is conducted again, such memory cell can be discriminated from the memory cell that is recovered as a normal cell after the write operation is conducted again.
The status register has the fourth bit indicating whether the threshold voltage of the memory cell to which the write operation is conducted exceeds or not the upper limit value or lower limit value of the predetermined voltage range of the threshold voltage corresponding to the writing condition. Accordingly, whether the threshold voltage of the memory cell generating a write error has exceeded the upper limit value or lower limit value can be discriminated and fault analysis can be realized very easily.
The memory cell explained above is constituted to store the information of three or more levels depending on the threshold voltage and the fourth bit explained above is composed of a plurality of bits indicating whether the fourth bit exceeds or not the predetermined voltage range corresponding to respective threshold voltages. Accordingly, it is now possible, in the memory device that can store multi-level information with the memory cell, to know which voltage range the threshold voltage of the memory cell having generated the verify error has exceeded and the fault analysis can be executed easily.
Contents of the status register are outputted to the external terminal when a plurality of control signals supplied from the external side of the chip are combined as specified. Accordingly, it is no longer required to provide a new control signal to read the contents of the status register.
Here, it is preferable to provide a structure that the condition of the first bit of the status register is always outputted to the exclusive external terminal of the chip. Accordingly, it can always be detected that the external control device such as CPU for making access to the relevant memory device can make access or not.
Moreover, contents of the status register is outputted to the external terminal that is used in common for the input of the write information supplied from the external side of the chip. Accordingly, the number of external terminals required for the relevant memory device can be reduced.
It is also possible that contents of the status register is outputted to the external terminal that is used in common for the input of the write address supplied from the external side of the chip. Accordingly, the number of external terminals required for the relevant memory device can further be reduced.
Here, a control circuit for executing the process based on a command code supplied from the external circuit is provided and a control signal for the internal circuit corresponding to the command code is formed. Accordingly, the status register is provided within this control circuit. Accordingly, the internal condition can easily be reflected on the status register.
Another invention of the present patent application is a non-volatile semiconductor device comprising a plurality of memory cells for changing the threshold voltage by applying the predetermined voltage to the selected memory cell and then storing the information depending on difference of the threshold voltages and a status register for indicating the internal condition of chip, whereby write operation to the memory cell is conducted by once erasing the threshold voltage of the selected memory cell and then changing such threshold voltage to the voltage corresponding to the write condition depending on the write information. After the threshold voltage is changed to the voltage corresponding to the erasing condition, whether the threshold voltage of the selected memory cell has exceeded or not the predetermined voltage range is determined; when the threshold voltage exceeds the predetermined voltage range, the condition indicating an error is set to the first bit of the status register; after the threshold voltage is changed to the voltage corresponding to the write condition depending on the write information, whether the threshold voltage of the selected memory cell has exceeded or not the upper limit value (or lower limit value) of the predetermined voltage range is determined; when the threshold voltage exceeds the predetermined range, the condition indicating an error is set to the second bit of the status register; after above determination, whether the threshold voltage of the selected memory cell exceeds or not the lower limit value (or upper limit value) of the predetermined voltage range is determined; when the threshold voltage does not exceed the predetermined range, the condition indicating an error is set to the third bit of the status register. Moreover, when the threshold voltage of the selected memory cell does not exceed the lower limit value (or upper limit value) of the predetermined voltage range, the write process is executed again. If the threshold voltage of the selected memory cell does not yet exceed the lower limit value (or upper limit value) of the predetermined voltage range even after the repeated write operation, the condition indicating an error is set to the fourth bit of the status register. Accordingly, setting of each bit forming the status register can be realized very effectively.
Moreover, the status register explained above also has the fifth bit for indicating whether access is possible or not from the external side of the chip and sets this fifth bit, on the occasion of starting the write operation, to the condition for inhibiting the access from the external side of the chip and also sets this fifth bit, after the above write operation and the setting of the first to fourth bits, to the condition for allowing access from the external side of the chip. In addition, condition of this fifth bit is always outputted to the exclusive external terminal. Accordingly, whether the relevant memory device is in the accessible condition or not can be quickly and accurately reflected on the status register.